1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having a circuit structure for maintaining the level of a boosted signal line and a word driver connected to the boosted signal line, and a redundancy structure.
2. Description of the Background Art
FIG. 21 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 21, a semiconductor memory device of a dynamic RAM includes a memory array 161, a row address buffer 164, a row decoder 163, word drivers 162a-162h, a column address buffer 167, a column decoder 166, a sense amplifier 165, an input/output circuit 168, and a control circuit 169. Memory array 161 has bit lines and word lines disposed vertically and horizontally therein. Row address buffer 164 receives an externally applied row address. Row decoder 163 receives an output of row address buffer 164. Word drivers 162a-162h respond to an output of row decoder 163 to drive a word line. Column address buffer 167 receives an externally applied column address. Column decoder 166 receives an output of column address buffer 167. Sense amplifier 165 responds to an input from column decoder 166 to amplify a small current of memory array 161. Input/output circuit 168 carries out input/output of data with sense amplifier 165 via an I/O line. Control circuit 169 receives a row address strobe signal (/RAS), a column address strobe signal (/CAS), and a read/write control signal (W) to control the above device.
The operation of this semiconductor memory device will be described hereinafter. In response to an output of row address buffer 164 to which a row address is input, row decoder 163 selects a word line corresponding to a specified row address. For example, in FIG. 21, when the top most word line is selected, word driver 162a pulls up that word line. Then, sense amplifier 165 operates, whereby a small current read out from a memory cell at the crossing of a bit line and a word line in memory array 161 is amplified. In response to an output of column address buffer 167 to which a column address is input, column decoder 166 selects a bit line pair. The selected bit line pair is connected to an I/O line connected between input/output circuit 168 and sense amplifier 165. The data on the I/O line is amplified by a preamplifier in input/output circuit 168 to be transmitted to an output buffer for a read out operation. Externally applied data is transferred to the I/O line by a write buffer of input/output circuit 168 for a write operation.
There are some semiconductor memory devices that have a spare memory cell arranged besides memory array 161 of N (=nxm) bits for exchange of a defective bit.
In general, a memory cell includes a capacitor and an n channel MOS transistor. One electrode of the capacitor is fixed to a potential 1/2 Vcc which is half the power supply potential Vcc. The n channel MOS transistor has the gate electrode connected to a word line. The n channel MOS transistor is connected to the other electrode of the capacitor and a bit line. A predetermined potential is maintained at the other electrode of the capacitor to store data. When power supply potential V.sub.CC is to be transferred from a bit line to the other electrode of the capacitor without a voltage drop of the threshold voltage Vth of the n channel MOS transistor, a potential of a V.sub.PP level that is higher than V.sub.CC +V.sub.th must be supplied from the word line to the gate electrode of this n channel MOS transistor. A semiconductor memory device that needs a potential of such a V.sub.PP level will be described hereinafter.
FIG. 22 is a block diagram of the main components of the semiconductor memory device of FIG. 21. FIG. 23 is a circuit diagram of the word driver of FIG. 22.
Referring to FIGS. 22 and 23, submemory arrays 171a and 171b are separated by a sense amplifier 172. At one side of submemory arrays 171a and 171b, row decoders 173a and 173b are provided, respectively. 4 n word lines are provided between row decoder 173a and submemory array 171a, and also between row decoder 173b and submemory array 171b. A word driver is provided at each word line. For example, word drivers 174a, 174b, 174c and 174d are provided at the upper 4 word lines disposed between row decoder 173a and submemory array 171a. Word drivers 175a, 175b, 175c and 175d are provided at the upper 4 word lines disposed between row decoder 173b and submemory array 171b. Boosted signal lines are disposed in the vertical direction with respect to the word lines disposed in the horizontal direction in the drawing.
The boosted signal line to which a boosted decode signal RX.sub.1 is input is connected to word drivers 174a and 175a. The boosted signal line to which a boosted decode signal RX.sub.2 is input is connected to word drivers 174b and 175b. The boosted signal line to which a boosted decode signal RX.sub.3 is input is connected to word drivers 174c and 175c. The boosted signal line to which a boosted decode signal RX.sub.4 is input is connected to word drivers 174d and 175d.
In other words, word lines are disposed so that word drivers 174a and 175a provided at the topmost word lines in submemory arrays 171a and 171b, respectively, receive boosted decode signal RX.sub.1 ; word drivers 174b and 175b provided at the respective second word lines receive boosted decode signal RX.sub.2 ; word drivers 174c and 175c provided at the respective third word lines receive boosted decode signal RX.sub.3 ; and word drivers 174d and 175d provided at the respective fourth word lines receive boosted decode signal RX.sub.4. Also, the word driver provided at the fifth word line receives boosted decode signal RX.sub.1, and the word driver provided at the sixth word line receives boosted decode signal RX.sub.2. Such boosted decode signals are repeatedly input to the word drivers.
In addition to a boosted decode signal, each word driver receives an output (signals WD, ZWD) of the row decoder.
As shown in FIG. 23, word driver 174 includes an n channel MOS transistor (N1) 181a, an n channel MOS transistor (N2) 181b, and an n channel MOS transistor (N3) 181c. n channel MOS transistor 181a functions as a transfer gate. A signal WD which is decoded to a level in row decoder 173a is applied to one of the source/drain thereof. Power supply voltage Vcc is applied to the gate thereof. n channel MOS transistor 181b receives boosted decode signal RX.sub.1 at its drain and an output of n channel MOS transistor 181a at its gate. n channel MOS transistor 181c has its gate supplied with an inversion signal ZWD of signal WD which is decoded to a level by row decoder 173b, and its source supplied with ground potential GND. The drain of n channel MOS transistor 181c is connected to the source of n channel MOS transistor 181b.
The operation thereof will be described hereinafter. Signal WD which is decoded to a certain level in row decoder 173a and an inversion signal thereof ZWD are input to the word driver provided at each word line. When each word driver attains a standby state (de-select state), signal WD attains a L level and inversion signal ZWD attains a H level. Therefore, n channel MOS transistor 181b is turned off, and n channel MOS transistor 181c is turned on. Therefore, word line WL is pulled to ground potential GND by n channel MOS transistor 181c, and is not activated.
When signal WD attains a H level, a node A is charged to the level of V.sub.CC -V.sub.th which is power supply voltage V.sub.CC minus the threshold voltage via n channel MOS transistor 181a. Because inversion signal ZWD attains a L level when signal WD attains a H level, n channel MOS transistor 181c is off, and word line WL is not connected to ground potential GND. When node A is charged and the boosted level of the decoded boosted decode signal RX.sub.1 is applied to the drain of n channel MOS transistor 181b, node A is boosted by the coupling of the gate and drain, i.e. self boosted, so that n channel MOS transistor 181b is deeply turned on. As a result, word line WL is sufficiently charged to the boosted level to be selected. Therefore, access to a memory array is allowed.
A word line is selected to be pulled up only when signal WD and boosted decode signal RX.sub.l both attain a H level. The word line will not be selected in other combinations since it is not pulled up. In other words, decoding is also carried out in a word driver.
FIG. 24 shows the addition of a spare submemory array including a spare memory cell to be exchanged for a defective memory cell in the memory array of FIG. 22. In FIG. 24, elements corresponding to those of FIG. 22 have the same reference characters denoted, and their description will not be repeated.
Referring to FIG. 24, a spare memory cell array 191a is provided between memory cell array 171a and sense amplifier 172. A spare submemory array 191b is provided between submemory array 171b and a sense amplifier not shown. At one side of spare submemory arrays 191a and 191b, corresponding spare row decoders 192a and 192b are provided. A spare word line is disposed between spare row decoder 192a and spare submemory array 191a, and between spare row decoder 192b and spare submemory array 191b.
Spare word drivers 193a, 193b, 193c, and 193d are provided at respective spare word lines in order from the topmost spare word line disposed between spare row decoder 192a and spare submemory array 191a. Spare word drivers 194a, 194b, 194c and 194d are provided at respective spare word lines provided between spare row decoder 192b and spare submemory array 191b. Spare word drivers 193a and 194a provided at the respective topmost spare word lines receive boosted decode signal RX.sub.1. Spare word drivers 193b and 194b provided at the second spare word lines receive boosted decode signal RX.sub.2. Spare word drivers 193c and 194c provided at the third spare word lines receive boosted decode signal RX.sub.3. Spare word drivers 193d and 194d provided at the fourth spare word lines receive boosted decode signal RX.sub.4.
When a fault is generated in a memory cell in, for example, submemory array 171a, a fuse 195a provided in spare row decoder 192a is blown out. In response, the row address corresponding to the defective memory cell is substituted for the row address corresponding to a spare memory cell in spare memory array 191a to carry out exchange. Each of the structure of spare word drivers 193a-193d, 194a-194d is similar that of the word driver shown in FIG. 23, and their description will not be repeated.
There are semiconductor memory devices that use boosted voltage instead of a decode boosted signal. FIG. 25 is a block diagram of such a semiconductor memory device. FIG. 26 is a circuit diagram of a word driver shown in FIG. 25.
Referring FIGS. 25 and 26, submemory arrays 201a and 201b are divided by a sense amplifier 202. At one side of submemory arrays 201a and 201b, corresponding row decoders 203a and 203b are provided. A plurality of word lines are disposed between row decoder 203a and submemory array 201a with word drivers 205a-205h respectively. Similarly, a plurality of word lines are disposed between row decoder 203b and submemory array 201b with word drivers 206a-206h respectively.
Word drivers 205a-205h are connected to the same segment boosted signal line 207a. One end of segment boosted signal line 207a is connected to one of the source/drain of switching transistor 204a. The gate of switching transistor 204a receives a control signal .phi..sub.1. The other source/drain of switching transistor 204a is connected to a global boosted signal line 208a having a potential level of boosted voltage V.sub.PP. In response to control signal .phi..sub.1, switching transistor 204a is turned on/off, whereby boosted voltage V.sub.PP is supplied to each of word drivers 205a-205h via segment boosted signal line 207a.
Similarly, word drivers 206a-206h are connected to a same segment boosted signal line 207b. The other end of segment boosted signal line 207b is connected to one source/drain of switching transistor 204b. The gate of switching transistor 204b receives a control signal .phi..sub.2. The other source/drain of switching transistor 204b is connected to a global boosted signal line 208b having a boosted voltage V.sub.PP. Global boosted signal lines 208a and 208b are eventually connected to a V.sub.PP generation circuit not shown for generating boosted voltage V.sub.PP.
Word drivers 205a-205h and 206a-206h receive, not only boosted voltage V.sub.PP transmitted via switching transistor 204a and 204b, but also an inversion signal ZWD which is a signal completely decoded by row decoders 203a and 203b and converted into a boosted level. For example, word driver 205 includes a p channel MOS transistor (P1) 211, and an n channel MOS transistor (N1) 212, as shown in FIG. 26. p channel MOS transistor 211 has its gate supplied with decode signal ZWD, and its source connected to segment boosted signal line 207a. n channel MOS transistor 212 has its gate supplied with decode signal ZWD, and its source connected to ground potential GND. Thus, word driver 205a is formed as a CMOS inverter circuit that operates between a supplied boosted potential V.sub.PP and ground potential GND.
An operation of particularly submemory array 201a will be described hereinafter.
When control signal .phi..sub.1 attains a level of boosted voltage V.sub.PP, switching transistor 204a is off. Therefore, boosted voltage V.sub.PP is not supplied to each of word drivers 205a-205h. When control signal .phi..sub.1 attains the level of ground potential GND, switching transistor 204a is on. Boosted voltage V.sub.PP is supplied to each of word drivers 205a-205h via segment boosted signal line 207a when switching transistor 204a is on.
When signal ZWD output from row decoder 203a attains the level of boosted voltage V.sub.PP, p channel MOS transistor 211 is off and n channel MOS transistor 212 is on. Therefore, word line WL is pulled down to ground potential GND by n channel MOS transistor 212 to attain a standby (de-select) state. When signal ZWD attains a L level, n channel MOS transistor 212 is off and is not in conduction with ground potential GND. Therefore, p channel MOS transistor 211 attaining an on state causes word line WL to be charged sufficiently to the level of boosted potential V.sub.PP. Thus, a sufficiently charged word line WL is selected.
There are also semiconductor memory devices that have switching transistors removed, as shown in FIG. 27. Boosted voltage V.sub.PP is directly applied to a word driver via a global boosted signal line 221.
In recent years, the circuit complexity has increased as the memory capacity becomes greater, resulting in increase of the consumed current. It is envisioned that consumed current can be suppressed if the circuit complexity is simplified. However, such simplification in circuitry should not cause reduction in reliability thereof. It is also important to speed access in a semiconductor memory device. Furthermore, the exchange efficiency of a spare memory in the case of a fault in a submemory array and the chip area of the spare submemory array are also important factors. A semiconductor memory device with a high exchange efficiency and a small chip area is desired.
Here, exchange efficiency refers to the unit of a group of memory cells that are exchanged in using one spare submemory array when a defective submemory cell is exchanged for a proper spare memory cell. This means that a large group requires a larger memory capacity on the basis of a spare submemory array with respect to one exchange. This will cause increase in the chip area of the spare submemory array.
In recent years, a semiconductor memory device that carries out exchange, not in the unit of word lines as shown in FIG. 24, but in the unit of submemory arrays, has attracted a lot of attention. Such a semiconductor memory device is disclosed in the Journal of Technical Papers of ISSCC 93, pp. 48-49.
However, conventional semiconductor memory devices have problems set forth in the following.
In the semiconductor memory device shown in FIG. 25, when submemory array 201a is de-selected, and switching transistor 204a attains a non-conductive state, charge will leak from segment boosted signal line 207a via each of word drivers 205a-205h due to subthreshold leakage current therein. This causes reduction in potential of segment boosted signal line 207a from the level of boosted potential V.sub.PP. When submemory array 201a is selected and transistor 204a is conductive, segment boosted signal line 207a must be boosted up to the level of boosted potential V.sub.PP again. If the potential of segment booted signal line 207a was lowered to a level in the vicinity of ground potential, the boosting up to the level of boosted potential V.sub.PP will be time consuming, resulting in a slow access time.
Furthermore, in a semiconductor memory that carries out exchange in the unit of submemory arrays, a submemory array is directly exchanged with a spare submemory array. Therefore, the exchange efficiency is low. Furthermore, it is difficult to increase the number of spare submemory arrays from the standpoint of the chip area. Therefore, it was difficult to improve the yield.
There are also problems in a semiconductor memory device that carries out exchange in a word line unit as shown in FIG. 24. When leakage occurs in a segment boosted signal line due to a defective word line, all the word lines associated with that segment boosted signal line will also become defective. Therefore, the exchange efficiency will become the same as that of exchange carried out in the unit of submemory arrays.
In the semiconductor memory device of FIG. 25, the transition rate of a word driver from a standby state to an active state depends upon the potential of a segment boosted signal line. More specifically, when a switching transistor is off, the potential will become as low as the level of ground potential in the worst case due to junction leakage and subthreshold leakage. During the time period of the potential of the segment boosted signal pulled up to the level of boosted potential V.sub.PP, the word driver cannot attain an active state. Therefore a high speed operation could not be carried out.
In the semiconductor memory device shown in FIG. 27 where switching transistors are removed and boosted voltage V.sub.PP is supplied directly from global boosted signal line 221 to a word driver, there is a problem that the consumed current becomes so great that it causes standby current fault when current begins to leak from global boosted signal line 221 due to a fault in a word driver. When the word driver shown in FIG. 26, for example, is applied to the semiconductor memory device shown in FIG. 27, such a fault with respect to a word driver includes the generation of a great leakage current due to a great potential difference between a boosted voltage V.sub.PP and ground voltage GND applied on p channel MOS transistor 211. Furthermore, the output of the row decoder applied to the word driver must be completely decoded, causing increase in the circuit complexity of the row decoder. This results in a problem that the layout pitch is reduced with respect to a row decoder.
In the word driver of FIG. 23, if the self boost by means of coupling at n channel MOS transistor 181b is not sufficient, the selected word line will not have a sufficient level to be driven. This results in an insufficient opening of the transfer gate to cause erroneous operation. Adjustment was made to carry out a complete self boost by delaying boosted decode signal RX.sub.1 by delay means. However, the delay time by the delay means varies due to a change in the process, resulting in the possibility of an erroneous operation. Increase in the delay time of boosted decode signal RX slows the access time. It is extremely difficult to design the timing in which a complete self boost is carried out without delay.
When boosted decode signal RX.sub.1 is applied to n channel MOS transistor 181b with node A at the level of V.sub.CC -V.sub.th, the potential of word line WL will rise only to the level of V.sub.CC -V.sub.th. It is therefore necessary to input boosted decode signal RX.sub.1 after node A is sufficiently charged. More specifically, it is necessary to carry out the so-called double boosting for node A to be boosted to the level of V.sub.CC +V.sub.PP -V.sub.th to transmit boosted voltage V.sub.PP of the boosted decode signal to word line WL. However, a great potential difference is applied between the source and gate of n channel MOS transistor 181b, resulting in the possibility of the reliability of n channel MOS transistor 181b being degraded.